Natwerk Designs

Digital logic EEPROM?

Hey guys, I have a professor at college who assigns labs without EVER teaching the subject. This lab we were supposed to construct a traffic light for a "main street" that is intersected by a "cross street". The light goes yellow asynchronously when an emergency vehicle comes from the cross street, and stays yellow for 1 clock after, followed by red for 2 clocks and back to green. It is also supposed to check every 5 cycles whether there is a car waiting at the cross street and if there is, it goes yellow for 1 cycle then red for 2, then back to green again. I did all that fine and I even constructed my own components using vhdl, but now they are asking me to create a second design using a 2865 EEPROM by hand. I know what an eeprom is, I do not know how it works, all I know is that the 2865 has 13 addresses and 8 outputs, I don't even know how the outputs are selected. Can anyone enlighten me? Sorry, I have to implement it using hand drawn gates....at least to my understanding I do (the professor explains nothing! and TAs dont respond to emails), but I don't see why I couldnt just write A0=(whatever) A1=(whatever). I do have a logic table because I essentially created the device before using 3 d flip flips and two sets of combinational logic. (Total amount of states equates to 7, so I only needed 3) So I used an ASM table to try and help me out, which it did. I just have no idea how the eeprom works though, I mean I originally thought it was just a big decoder, but I don't even know anymore. All I know is that the lowest address is o/o/o/o in hex and 1/f/f/f is the highest but I don't know what that means. does 0/0/0/0 select d0? and if 1/f/f/f is the highest, what output does that goe too since there are only 8 outputs (1000 base 2)

Public Comments

1. Hi there An EEPROM is similar to any ROM read only memory. The EEP prefix just means that its electrically erasable programmable ROM. So what this essentially says about the device is the way it can be programmed and erased and hence does not have any implications on the way the logic design is to be done. Can you please clarify if you need to implement the cricuit in a HDL like( VHDL or verilog ) or implement it using read devices. In the second case this would mean that the way you prgram would be different and you would require a compatable EEPROM and its programmer. As far as implemetation in HDL is concerned, you can download the data sheet of any EEPROM and write a simple behavioral model using the specifications. Or mostly you can find free beahvioral models avaiable for simple EEPROM devices. I dont think the prof expects you to write anything more than a behavioral model. Usually in HDL's memories are simulated by their behavioral models duing simulation phase. and when dowloading onto a device special library definitons are used (they are different for FPGA and ASIC). For FPGA's they are generated using a option in the IDE for the FPGA. In case you are confused on who to implement the logic using just memory I will give you a hint. Try writing down the truth table and considre the address inputs of the ROM as the input signals. Since a memory is essentaially asynchrosnous you might need some supporting sequential logic to satisfy your clocked requirements and then drive the memory from them Hope this helps